JPS6331816B

• Main Author: OOSHIMA YOSHIO
• Format: Patent
• Language: English
• Published: 27.06.1988
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PURPOSE:To decrease an address conversion overhead, by installing an address selecting circuit to select an address designation bit and a logic address data bit for a logic address and an address selection register to give the selection information and setting the selection information optionally. CONSTITUTION:An address selecting circuit 15 divides the bit groups within a logic address register 2 into an address designation bit group (a) and a logic address data bit group (b) based on the selection information given from an address selection register 14 then output them. The contents of the register 14 is set by a register setting instruction during an application of power source, a switch of program, etc. At that point of time, the contents of an address selection buffer 5 becomes ineffective. A logic address is transferred to the register 2 when a memory reference is requested. Then the corresponding contents is divided into (a) and (b) by the buffer 15, the buffer 5 is refered to (a). Thus a registered logic address (c) and a registered real address (d) are read to registers 6 and 7. The contents of the register 6 is compared 8 with (b). When they coincide, the contents of the register 7 is identical with the desired real address.