MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE:To obtain a multilayer interconnection having an excellent step coverage, by heating an SOG film by high frequency induction heating the SOG film is burned. CONSTITUTION:A fist Al wiring layer 3 is formed by patterning an Al layer on a silicon oxide film 2. An interlayer insulating film 4 co...

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Bibliographic Details
Main Author AKAISHI YOSHIO
Format Patent
LanguageEnglish
Published 28.10.1988
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Summary:PURPOSE:To obtain a multilayer interconnection having an excellent step coverage, by heating an SOG film by high frequency induction heating the SOG film is burned. CONSTITUTION:A fist Al wiring layer 3 is formed by patterning an Al layer on a silicon oxide film 2. An interlayer insulating film 4 consisting of a silicon oxide film is formed so as to cover the wiring 3. A material for an SOG film 5 is applied to the entire surface by an ordinary spin coating. High frequency induction heating is utilized for burning the SOG film 5. Thus the entire SOG film 5 can be heated at the uniform temperature. In this way, the SOG film 5 without burning irregularities can be formed. Therefore, the uniform film, in which difference in etching rate is not yielded with respect to etching liquid for providing a hole in the SOG film 5, is obtained, and a rat tunnel can be prevented. Thus a contact hole 7 can be tapered by the combination of wet etching and dry etching.
Bibliography:Application Number: JP19870095561