INFORMATION PROCESSOR

PURPOSE:To expand addresses or operand data while keeping interchangeability with ordinary instruction formats by deciding the expansion of operand addresses and data at the time of decoding an instruction. CONSTITUTION:When an instruction is set in an instruction register 2, its operation code and...

Full description

Saved in:
Bibliographic Details
Main Author NAGAI SEIJI
Format Patent
LanguageEnglish
Published 05.08.1988
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:PURPOSE:To expand addresses or operand data while keeping interchangeability with ordinary instruction formats by deciding the expansion of operand addresses and data at the time of decoding an instruction. CONSTITUTION:When an instruction is set in an instruction register 2, its operation code and mode are checked by a decoding/mode checking circuit 20 and a prescribed value is set in an address/data expansion information register 21. On the other hand, an operand address formed by an address computer 8 is set in an address register 10. At that time, '0' is set in a high-order prescribed bit of the register 10 in accordance with the value of a register 211 corresponding to an operand fetch in the register 21. Thus, the addresses or operand data can be expanded while keeping interchangeability with the ordinary instruction formats.
Bibliography:Application Number: JP19870021972