DATA PROCESSOR

PURPOSE:To minimize the increase of an undesired load on an internal data bus and to improve the efficiency of data transfer by increasing relatively the number of bits of the internal bus which connects a processor to each function block in response to connected areas. CONSTITUTION:An internal data...

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Bibliographic Details
Main Author KIHARA TOSHIMASA
Format Patent
LanguageEnglish
Published 25.07.1988
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To minimize the increase of an undesired load on an internal data bus and to improve the efficiency of data transfer by increasing relatively the number of bits of the internal bus which connects a processor to each function block in response to connected areas. CONSTITUTION:An internal data bus IDB connected with a microprocessor MPU is connected to a function block of a 1st data memory DTM, etc., that is required for the relatively high-speed transfer of data to the MPU via an area of 16 bits. Thus reading/writing actions are carried out every 16 bits to such a function block requiring the high-speed transfer of data in case the MPU accesses said function block. As a result, the data transfer frequency is halved to improve the data transfer efficiency in comparison with a case where the bus IDB has single bit constitution of 8 bits. The area where the number of bits is increased is limited at a position between those function blocks requiring the high-speed transfer of data. Therefore, the area efficiency is never affected at all.
Bibliography:Application Number: JP19870009801