MEMORY CONTROL CIRCUIT

PURPOSE:To improve the processing speed of the titled circuit by detecting the boundary of an address of a maximum capacity of a data transferred at once from a CPU to a memory so as to count up an address boundary space. CONSTITUTION:A CPU is connected to a memory having a memory area larger than t...

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Bibliographic Details
Main Author KAWASHIMA SHINICHIRO
Format Patent
LanguageEnglish
Published 31.05.1988
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To improve the processing speed of the titled circuit by detecting the boundary of an address of a maximum capacity of a data transferred at once from a CPU to a memory so as to count up an address boundary space. CONSTITUTION:A CPU is connected to a memory having a memory area larger than the address width of the CPU via a system bus and a memory controller makes all addresses of the memory addressable. Prior to the data transfer, the CPU outputs an address to an I/O latch and uses an output of a NAND2 to clear a F/F2 simultaneously. Then the data is transferred and subject to the processing of NAND1 with the output of the CPU to change the state of the outputs Q, inverse of Q of the F/F2, holds it during a prescribed output of the CPU, the boundary of the address transferred to the memory is detected and the address boundary space is counted up by a full adder to improve the processing speed.
Bibliography:Application Number: JP19860274430