JPS6240914B

PURPOSE:To fetch accurately a desired still picture signal to a CPU in synchronization with another still picture signal and to perform the arithmetic processing, by applying an interruption to the CPU for each input of the still picture signal. CONSTITUTION:The pulses outputted from a timing signal...

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Bibliographic Details
Main Authors HIRAMATSU KYOSHI, TAKEZAWA TERUHIRO, HIRAHATA SHIGERU
Format Patent
LanguageEnglish
Published 31.08.1987
Subjects
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CRYPTOGRAPHY
DISPLAY
EDUCATION
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
SEALS
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Summary:PURPOSE:To fetch accurately a desired still picture signal to a CPU in synchronization with another still picture signal and to perform the arithmetic processing, by applying an interruption to the CPU for each input of the still picture signal. CONSTITUTION:The pulses outputted from a timing signal generating circuit 16 only in the 20th and 283rd H are inverted by an NOT circuit 28 of a sensor circuit 19 and outputted to the reset input of an FF circuit 27 to release the reset state of the circuit 27 just for that period. The input still picture signal is supplied to the reset input of the circuit 27 and therefore the circuit 27 is set usually for about 1H and then reset at the end of the 20th or 283rd H. The positive logic output signal of the circuit 27 is used as it is to the output signal of the circuit 19, then outputted to a CPU18 as an interruption signal.
Bibliography:Application Number: JP19840153011