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PURPOSE:To obtain a screen that does not cause a viewer to feel uncomfortable with lowering the luminance of the screen or interrrupting an output signal itself by deciding whether it is a pull in state or not by the logical product of the reset signal of a divider in a vertical synchronous circuit...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
07.02.1987
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Subjects | |
Online Access | Get full text |
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Summary: | PURPOSE:To obtain a screen that does not cause a viewer to feel uncomfortable with lowering the luminance of the screen or interrrupting an output signal itself by deciding whether it is a pull in state or not by the logical product of the reset signal of a divider in a vertical synchronous circuit and the logic OR of two control signals in an internal oscillator control circuit. CONSTITUTION:An inverter 20 inverts the reset signal that resets a frame counter 8. It is assumed that the inverted reset signal 21 is the first unlock detecting signal. A NOR gate circuit 22 takes the negation of the logic OR of two control signals that controls an updown counter 11. It is assumed that the output 23 in the second unlock detecting signal. In other words, the detecting signals 21 and 23 become zero in an unlock time. A logical circuit 24 generates the third unlock detecting signal 25 from previous stated two unlock detecting signals, and it is constituted that the output 25, when it is zero, is inverted to one when both of inputs 21 and 23 become one, and adversely, the output 25, when it is one, is inverted to zero when the input 21 becomes zero, regardless of the state of the input 21. |
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Bibliography: | Application Number: JP19850167919 |