MEMORY SYSTEM

PURPOSE:To attain high speed with a low voltage and low power consumption and to design the size of a memory cell to a small size by providing a memory array connected to a data line and a bus line and storing station numbers by one station at every digit. CONSTITUTION:The titled system comprises a...

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Bibliographic Details
Main Authors MASUDA EIJI, TAKASAKI TERUFUMI, FUJITA YASUHIKO
Format Patent
LanguageEnglish
Published 29.01.1987
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
TELEPHONIC COMMUNICATION
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Summary:PURPOSE:To attain high speed with a low voltage and low power consumption and to design the size of a memory cell to a small size by providing a memory array connected to a data line and a bus line and storing station numbers by one station at every digit. CONSTITUTION:The titled system comprises a Y address decoder designating station addresses to which plural digits of station numbers are stored, an X address decoder designating digit addresses to which each digit of the station numbers is stored, the memory array 100 where memory cells corresponding to the station addresses and digit addresses are arranged, a data line 60 transmitting/receiving data to a memory cell corresponding to a designated station address and a temporary memory connected to the bus line 40 and the data line 60 and storing station numbers by one station at every digit. Then data between the bus line and the memory array is transmitted/received via the temporary memory at the designation of a station address. Thus, high speed operation is attained with a low voltage and low power consumption and the size of the memory cell is decreased.
Bibliography:Application Number: JP19850161626