SEMICONDUCTOR TESTING DEVICE

PURPOSE:To generate an algorithmic pattern for a complicate function test at a high speed by detecting the parity of an optional bit group of an ALU output register and shifting the detection result in an ALU. CONSTITUTION:The contents of the ALU output register 5 are ANDed with the contents of a bi...

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Bibliographic Details
Main Authors MAENO HIDESHI, TADA TETSUO
Format Patent
LanguageEnglish
Published 28.08.1987
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:PURPOSE:To generate an algorithmic pattern for a complicate function test at a high speed by detecting the parity of an optional bit group of an ALU output register and shifting the detection result in an ALU. CONSTITUTION:The contents of the ALU output register 5 are ANDed with the contents of a bit selection register 6 and the result is sent to a parity detecting circuit 8. The circuit 8 detects the parity and supplies the result as a shift input to the ALU 3 with a shift-in function. In case a pseudo random number is generated, a proper value is set in the register to select bits supplied from the register 5 to a circuit and also specify shift arithmetic as the arithmetic of the ALU 3. Further, a selector 4 also specifies the side of the register 5. In this state, when this algorithmic pattern generating circuit is operated, the contents of the register 5 are shifted in order. Thus, the pseudo random number is generated at a high speed to take the function test of a semiconductor at a high speed.
Bibliography:Application Number: JP19860037745