SEMICONDUCTOR STORAGE DEVICE

PURPOSE:To reduce the stray capacity of a signal wiring and the interference between data lines and to realize a quick action by arranging a shift register between decoders astride a control signal wiring and transferring data through the decoders. CONSTITUTION:The shift register is configured with...

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Bibliographic Details
Main Authors OTA KIYOTO, KAWAI HIDEKI, MAEYAMA YOSHIKAZU, FUJII MASARU
Format Patent
LanguageEnglish
Published 22.08.1987
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Summary:PURPOSE:To reduce the stray capacity of a signal wiring and the interference between data lines and to realize a quick action by arranging a shift register between decoders astride a control signal wiring and transferring data through the decoders. CONSTITUTION:The shift register is configured with register parts 11-18, 21-28, 31-38 and 41-48, and data lines connected to the registers 11-48 is connected to a corresponding bit line through the decoder 3. A read control signal generator circuit block 61, a shift register control signal generator circuit block 62 and a write control signal generator circuit block 63 generate the signals of control signal lines 51, 52 and 53. With such block constitution the shift registers 11-48 are packed into one, whereby the control lines of the shift registers can use one system in common to substantially reduce the stray capacity of the wiring.
Bibliography:Application Number: JP19860034679