MOS TYPE SEMICONDUCTOR INTEGRATED CIRCUIT

• Main Authors: KAWAI HIDEKI, NISHIMOTO TOSHIO, YAMAZAKI HIROYUKI, SAKAGAMI MASAHIKO, FUJII MASARU
• Format: Patent
• Language: English
• Published: 18.08.1987
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

PURPOSE:To send accurately a logic signal by giving the 3rd control signal to the gate of the 1st transistor (TR) through a common control section between a gate and a drain of the 5th TR and the 2nd coupling capacitor. CONSTITUTION:When control signals S1, S2 to sequentially to a high level (power supply potential), the control signal S1 goes to the high level at first, a gate potential of a transistor (TR) T1 rises up to a potential of (VCC-VT) and a TR T2 is cut off. The control signal S2 goes to the high level just after the TR T2 is cut off, and the potential of the TR T1 goes to a level of over VCC+VT. In such a case, an electric charge is supplied from a power supply to the TR T1 by the operation of the TRs T3-T5, a control signal S3 and a capacitor C2, the potential of the TR T1 is kept for a long time while remaining at a level over VCC+VT and the TR T1 is conductive. Thus, a logic signal S0 is set accurately to the output side.