SEMICONDUCTOR MEMORY DEVICE

PURPOSE:To simplify bit line and make possible a high integration by commonly connecting gates of the third and the fourth N-type MOS transistors to a word line and connecting a drain of the fourth N-type MOS transistor to a bit line. CONSTITUTION:An N-type MOS transistor 4 is connected in parallel...

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Bibliographic Details
Main Authors OKABAYASHI ICHIRO, KADOTA HIROSHI
Format Patent
LanguageEnglish
Published 21.01.1987
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:PURPOSE:To simplify bit line and make possible a high integration by commonly connecting gates of the third and the fourth N-type MOS transistors to a word line and connecting a drain of the fourth N-type MOS transistor to a bit line. CONSTITUTION:An N-type MOS transistor 4 is connected in parallel with a resistance 5 and a gate of the transistor 4 is connected to a word line 8. In order to operate the conductor memory cell 9, a word line drive circuit 10 is connected to the word line 8 and a precharge circuit 11 and a sense amplifier 12 are connected to a bit line 7. During writing, the bit line 7 is fixed to High (5V) or Low (0V), a voltage is given to the word line 8 and a MOS transistor 3 is turned on. Through the transistor 3, the information of the bit line 7 is transmitted to a cell 9 and a voltage in the cell 9 is changed.
Bibliography:Application Number: JP19850151587