SYNCHRONIZING CLOCK SIGNAL GENERATOR

• Main Authors: UCHIMURA KIYOSHI, KITAURA HIROSHI
• Format: Patent
• Language: English
• Published: 20.01.1987
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

PURPOSE:To minimize the oscillation frequency variation of the output clock of a VCO by eliminating, by an LPF, the higher component of a nose when it occurres close to the band of the synchronizing signal in a video signal, and thereby suppressing the input-analog-voltage value of the VCO. CONSTITUTION:An A/D-converted digital signal is supplied to a video signal input terminal 101, and its higher component is removed by the LPF 102 and inputted to a phase detector 103. The phase detector 103 compares the horizontal synchronizing signal in the video signal and the HP pulse from an internal horizontal synchronizing pulse input terminal 104, detects the phase difference, and inputs it to an adder 105. The adder 5 adds this phase difference at every HP pulse as processing overflow, and supplies the result to one input of a comparator 107 as the phase detection value of the horizontal scanning period. To another input of the comparator 107, a reference value from a reference value input terminal 106 is supplied. The positive/negative difference signal from the comparator 107 is D/A-converted 108, and inputted to the VCO 109, to suppress its analog-voltage variation, and thereby to minimize the variation of the oscillation frequency of its output clock.