SEMICONDUCTOR PACKAGE STRUCTURE
PURPOSE:To improve the property of lift for thermal fatigue of a semiconductor package structure by a method wherein a semiconductor substrate and a dielec tric substrate are coupled using a solder having the structure, wherein the cir cumference of the alpha initial crystal, containing a specific w...
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Main Authors | , , , , |
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Format | Patent |
Language | English |
Published |
24.04.1986
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Subjects | |
Online Access | Get full text |
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Summary: | PURPOSE:To improve the property of lift for thermal fatigue of a semiconductor package structure by a method wherein a semiconductor substrate and a dielec tric substrate are coupled using a solder having the structure, wherein the cir cumference of the alpha initial crystal, containing a specific weight ratio of tin, lead for the remainder and having large grain diameter, is surrounded by the eutectic of relatively large grain diameter. CONSTITUTION:Solder is formed on the soldering electrode 4 located on the side of a silicon chip by performing a vapor-deposition method, and the composition of the solder is set at 50wt% of lead and 50wt% of tin. A silicon substrate 6 is plated in an electric surface, and a lead film 10 and a tin film 11 are fused. A chip-side solder 12 of almost globular shape is formed. An alumina-ceramic substrate side solder 13 consisting of 50wt% lead and 50wt% tin is formed on the surface of an alumina-ceramic substrate side soldered electrode 5. When the above is heated up again to the temperature a little higher than the liquid- phase temperature of the solder consisting of 50wt% lead and 50wt% tin in the furnace in the state wherein the chip-side solder 12 and the alumina-ceramic substrate side solder 13, a package structure is completed. |
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Bibliography: | Application Number: JP19840201708 |