SEMICONDUCTOR MEMORY

• Main Authors: TOYODA NOBUYUKI, KANAZAWA KATSUE, HOJO AKIMICHI
• Format: Patent
• Language: English
• Published: 29.03.1986
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

PURPOSE:To reduce a lowering and a delay of a signal voltage, enhance a reliability and make possible a high possible a high speed operation by using a D type FET as a column switch connected to a bit line. CONSTITUTION:In case where a memory cell M1 is selected and an electric potential VB is changed from 'H' level = VDD to 'L' level = VL, in a D type MESFET-Q13 in which 'H' is given to a gate, an electric current flows through a passage as shown in the figure. When 'L' is read, a voltage between a drain and a source in the D type MESFET-Q13 becomes VDS1, and this is a difference of electric potentials between a data line DL and a bit line BL. When a D type MESFET as a column switch, a change in a electric potential in the bit line BL is substantially transmitted to the data line DL as it is, so that the difference in the electric potential of 'H', 'L' on the data line DL is large and an effective information reading can be done. When writing the information, similarly, a transmission delay becomes small and an effective and high speed writing operation can be done.