JPS613114B

• Main Authors: YAMANOCHI KAZUAKI, TANAKA IZUMI, NISHIMOTO KEIJI
• Format: Patent
• Language: English
• Published: 30.01.1986
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE:To obtain an MOS transistor of laminate gate structure whose gate length is short, while the surface of the device is made flat, by forming a voltage feeding line of the semiconductor memory with no concavity being provided. CONSTITUTION:A P<+> type layer 2 is formed on the surface of a P type Si substrate and further an islandlike field SiO2 film 9 is provided on the layer 2 with a plurality of transistor-forming regions 10 and the voltage feeding line 11 cutting the former perpendicularly being exposed, and the ion is injected through the film 9 to form an element separating region 12 in the region 10. Moreover, on the line 11, the 1st multicrystal Si layer 4 which turns to be a floating gate is provided through the intermediary of an SiO2 film, and further on the layer 4, the 2nd multicrystal Si layer 6 which becomes a control gate is laminated also through the intermediary of an SiO2 film. Furthermore, common beltlike resist layers are provided, being positioned on both end parts of the film 9, etching is applied thereto, and thus the Si layers 4 and 6 are made to be of a laminate gate structure 14. After that, on the exposed part of the line 11 other than the above are formed wiring layers 15 of multicrystal Si.