SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To prevent a latchup phenomenon by forming a semiconductor region for connecting a reference voltage to an inner well region of the width size of an MISFET in a gate longitudinal direction, thereby stabilizing the potential of the well region. CONSTITUTION:A plurality of MISFETs are formed i...

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Bibliographic Details
Main Author OTA TATSUYUKI
Format Patent
LanguageEnglish
Published 27.09.1986
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE:To prevent a latchup phenomenon by forming a semiconductor region for connecting a reference voltage to an inner well region of the width size of an MISFET in a gate longitudinal direction, thereby stabilizing the potential of the well region. CONSTITUTION:A plurality of MISFETs are formed in a well region 2 formed on the main surface of a substrate 1, thereby forming, for example, a DRAM. Numeral 10a designates a reference voltage connecting semiconductor region which is formed on the main surface of the inner region 2 of the width size of the MISFET in a gate longitudinal direction. The region 10a is formed in a vacant space between semiconductor elements and particularly between a P-channel MISFET and an N-channel MISFET. The region 10a increases the number of connections with conductive layers applied with a reference voltage, and stably holds the prescribed potential at the region 2, thereby preventing a latchup phenomenon.
Bibliography:Application Number: JP19850058338