STACK OVERFLOW DETECTOR

PURPOSE:To detect a stack overflow by providing a function to identify the writing to a data area from the writing in a stack area. CONSTITUTION:An upper limit comparator 22 compares the value A delivered to an address bus 12 with the value Au of an upper limit register 20 while a signal is delivere...

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Bibliographic Details
Main Authors ANDOU MAKOTO, NAKANO YOSHIO
Format Patent
LanguageEnglish
Published 03.04.1985
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To detect a stack overflow by providing a function to identify the writing to a data area from the writing in a stack area. CONSTITUTION:An upper limit comparator 22 compares the value A delivered to an address bus 12 with the value Au of an upper limit register 20 while a signal is delivered to a stack operation detecting signal line 25. Then an overflow signal 1 is delivered when A>Au is satisfied. While a lower limit comparator 23 compares the value A delivered to the bus 12 with the value Al of a lower limit register 21 and delivers an underflow signal 1 with A<Al. Therefore, 1 is delivered to a stack overflow detecting signal line 30 from an OR gate 26 when A>Au or A<Al is satisfied with the value A of a subject address of a stack operation instruction. Thus a stack overflow can be detected.
Bibliography:Application Number: JP19830166411