JPS6053895B

PURPOSE:To change the address effective range of an instruction address and the effective range of an operand address at an address generation time by causing a control signal, which extends the operand from an mode control part, to generate another control signal which extends these ragnes. CONSTIT...

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Bibliographic Details
Main Authors MYADERA HIROO, URASHIRO TSUNEO, HAYASHI KENJI, IZUMI CHIKAHIKO
Format Patent
LanguageEnglish
Published 27.11.1985
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To change the address effective range of an instruction address and the effective range of an operand address at an address generation time by causing a control signal, which extends the operand from an mode control part, to generate another control signal which extends these ragnes. CONSTITUTION:Address data 16 from instruction fetch control part 22, address data 17 from operand fetch control part 23, and address data 18 from execution part 24 are inputted to the selector circuit of memory control part 25, and one of them is selected as address data 8 in a control circuit. When the reguest from control part 23 or execution part 24 is selected by priority order dtermination circuit 9, control signal 20 is issued, and control signal 12 which extends the operand from mode control part 21 generates a control signal, which extends ranges, by AND circuit 11. As a result, the address effective range of an instruction address and the address effective range of an operand address can be changed at an address generation time.
Bibliography:Application Number: JP19780001996