SEMICONDUCTOR MEMORY CIRCUIT

PURPOSE:To prevent the formation of a difference between the speed of response of memory cells in the right and the left of a word line selective circuit by changing the number of the memory cells in the right and the left of the word line selective circuit. CONSTITUTION:A word line selective circui...

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Bibliographic Details
Main Author WATANABE ATSUMI
Format Patent
LanguageEnglish
Published 12.11.1985
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:PURPOSE:To prevent the formation of a difference between the speed of response of memory cells in the right and the left of a word line selective circuit by changing the number of the memory cells in the right and the left of the word line selective circuit. CONSTITUTION:A word line selective circuit 3 is arranged where displaced to the right or the left from the center, and the titled circuit is constituted so that time constants constituted by output resistance ROL, ROR to memory cell arrays 1, 2 in the right and the left and the load of the arrays 1, 2 approximately equalize. The time constants of the right and the left of the arrays 1, 2 are each represented by CL(RL+ROL) and CR(RR+ROR), and the number of the arrays 1, 2 in the right and the left of the circuit 3 is changed so that several time constant equalizes. Accordingly, the circuit 3 is constituted at a position where retardation in the right and the left of a word line are arranged without being formed at a central section, thus eliminating the deterioration of electrical characteristics.
Bibliography:Application Number: JP19840084597