STATIC MEMORY CONTROL CIRCUIT

PURPOSE:To confirm the data normalcy with a static memory by using a data normalcy confirming/correcting circuit and making use of the refresh cycle of a dynamic memory to check the data contents. CONSTITUTION:When a refresh action is started with a dynamic memory STM, a counter CNT starts its count...

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Bibliographic Details
Main Author KANAZAWA NOBUHARU
Format Patent
LanguageEnglish
Published 24.01.1985
Edition4
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To confirm the data normalcy with a static memory by using a data normalcy confirming/correcting circuit and making use of the refresh cycle of a dynamic memory to check the data contents. CONSTITUTION:When a refresh action is started with a dynamic memory STM, a counter CNT starts its counting action and sends an address for the memory STM. In this case, the data is read out for each address of the memory STM by the prescribed signal supplied from a timing signal circuit TM and impressed to a data normalcy confirming/correcting circuit ECC. When an error is detected, the error information ERR is produced as an alarm. This information ERR is also fed back to a write/read terminal W/R of the memory STM as an error correction signal ERC. Thus the correction data is written. In such a way, the data contents are checked by making use of the refresh cycle of a dynamic memory and with addition of the circuit ECC. Thus the normalcy of data can be confirmed with a static memory.
Bibliography:Application Number: JP19830122020