DIGITAL PLL CIRCUIT

• Main Authors: SUZUKI KOUTAROU, KAMANAKA NOBUO
• Format: Patent
• Language: English
• Published: 27.07.1985
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

PURPOSE:To obtain a simple, small-scale PLL circuit by performing frequency division, phase operation, and phnase comparison by a ring counters composed of shift registers and a gate circuit. CONSTITUTION:A clock S6 of frequency which is six times as high as that of the input clock phiIN of an oscillator 6 is outputted. A change point detecting circuit 7 detects a change point of the input clock phiIN and outputs an edge signal S7. A phase difference detecting circuit 21 detects the phase difference between the input clock phiIN and ring counter 20 and decides that the input clock phiIN synchronizes with an output clock phiOUT when the edge signal S7 is 1 and the output Q of a flip-flop F3 is 1. At this time, inputs to a switch control circuit 8 are both 0 and the number of stages of the ring counter 20 does not change. When the edge signal S7 is 1 and a flip-flop F1 or F2 outputs 1, a step out occurs and the number of the stages of the ring counter changes, so that the output clock phiOUT follows up the input clock phiIN.