SEQUENTIAL DECODING CIRCUIT

• Main Author: KATOU MASAAKI
• Format: Patent
• Language: English
• Published: 09.07.1985
• Subjects: BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; INFORMATION STORAGE; INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PURPOSE:To reduce the number of shift registers to make sequential code conversion possible by storing every other bits of a data word, which is decoded from a code word and consists of plural bits, in a shift register where the code word is stored before decoding. CONSTITUTION:A decoded code word string is inputted from an input terminal 51 and is inputted to a shift register consisting of D flip-flops 55 and 56 through an inverter 53 and an NAND circuit 54 and is inputted to a D flip-flop 58 through an NAND circuit 57 and is inputted to a D flip-flop 60 from the D flip- flop 58 through an NAND circuit 59 and is inputted to an NAND circuit 61 from the D flip-flop 60 and is inputted to a D flip-flop 63 through an AND circuit 62. With respect to data bits, odd-numbered code bits are read out sequentially from the D flip-flop 63 by a D flip-flop 71 whose clock terminal the signal obtained by allowing the Q output of a D flip-flop 69 and the clock signal from a terminal 52 to pass an NAND circuit 70 is inputted to.