MICROPROGRAM ACCESS SYSTEM

PURPOSE:To attain reading of one machine cycle with no delay by using mainly a control memory at an intermediate speed to which an access is impossible in one machine cycle together with a partial use of a high-speed control memory to which an access is possible in one machine cycle. CONSTITUTION:Th...

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Bibliographic Details
Main Authors IWATA KATSUYUKI, INOUE KOUICHI, SAGARA HISAJIROU
Format Patent
LanguageEnglish
Published 10.06.1985
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To attain reading of one machine cycle with no delay by using mainly a control memory at an intermediate speed to which an access is impossible in one machine cycle together with a partial use of a high-speed control memory to which an access is possible in one machine cycle. CONSTITUTION:The contents A of a high-speed control memory HCS2 are read out in one machine cycle and set to a control memory data register CSDR4. Then the microcontrol is carried out according to the contents A. Then the contents A are read out of an even address bank LCSE31 in the next cycle and set to the CSDR4. Then the microcontrol is carried out according to the contents A. An address is fed to an LSC.O32 in the timing when an A(HCS) is read out to the CSDR4 and according to the contents B of an odd address register CSARO12. Then a microinstruction B is set to the CSDR4. At the same time, the O12 receives +1 and is set to CSARE11 as an address C. An access is fed to the bank E31. Hereafter LCS.E and LCS.O receive alternately accesses.
Bibliography:Application Number: JP19830212014