SEMICONDUCTOR MEMORY DEVICE

• Main Authors: FUTAMURA YASUO, NABEYA SHINJI
• Format: Patent
• Language: English
• Published: 04.06.1984
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PURPOSE:To enable to prevent the generation of the gate insulation breakdown of an address selecting MOSFET by providing a one directional element which transmits the potential of a semiconductor region to the side of a word line between the semiconductor region wherein a memory matrix is formed and the word line whereto the gate of the address selecting MOSFET is connected. CONSTITUTION:To prevent the generation of the gate insulation breakdown of the address selecting MOSFETQ2 of a memory cell MS at the time of erasure action, diodes D S1 and D S2 connected from the well region side toward the word line side are provided between the well region WELL and each of the first word lines W11 and W21. For these diodes D S1 and D S2, P-N junction diodes composed of the well region (P type) and an N<+> type region formed at the same time with an N<+> type semiconductor region which constitutes the source or drain of MOSFETQ1, Q2, etc. are utilized. Since the high voltage of the well region is transmitted to the first word lines W11 and W21 at the time of erasure action, the difference of potentials between the gate of the address selecting MOSFETQ2 and a substrate becomes almost the same potential; therefore the gate insulation breakdown thereof can be prevented.