MANUFACTURE FOR SEMICONDUCTOR DEVICE

• Main Author: NISHIMOTO KEIJI
• Format: Patent
• Language: English
• Published: 12.01.1983
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE:To obtain a tapered layer high in width-wise precision by a method wherein a polycrystalline Si layer with impurity density inclination is subjected to plasma etching and then to reactive ion etching, when a multiple layer wiring is fabricated using a polycrystalline Si layer. CONSTITUTION:An Si substrate 1 is covered with an SiO2 film 2 whereon a polycrystalline Si layer is grown and doped with P. The doping is done in two steps. First, an Si layer 23 is formed, rendered electroconductive by diffusion. Next, a highly doped layer 23' is formed, which is the topmost surface of the layer 23, with P ions implanted thereinto. The polycrystalline Si layer with density inclination thus caused is covered with a prescribedly patterned resist film 4. First, the layer 23' is subjected to plasma etching for the formation of side etches, which is followed by ion etching which forms a layer 23'' with a desired width. The existence of side etching prevents the generation in a PSG film 5 adhering on the whole surfaces, stepwise disconnection.