MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE:To connect between a lower layer wiring and an upper layer wiring with a wiring material buried in a through hole, to enhance yield of a wiring system, and moreover to hold the upper part of the through hole flat by a method wherein the PR process is supplemented by one process per one wirin...

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Main Author MIZUSHIMA KAZUYUKI
Format Patent
LanguageEnglish
Published 28.10.1983
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Abstract PURPOSE:To connect between a lower layer wiring and an upper layer wiring with a wiring material buried in a through hole, to enhance yield of a wiring system, and moreover to hold the upper part of the through hole flat by a method wherein the PR process is supplemented by one process per one wiring layer. CONSTITUTION:After a lower layer wiring 201 is formed on a semiconductor substrate 205, an interlayer insulating film 202 is adhered, the interlayer insulating film is etched using a resist 207 as the mask to open a through hole 206. At this time, the wiring material 208 of nearly the same thickness with the film 202 is adhered, and a resist 209 is formed only on the through hole. Then the wiring material 208 is removed leaving the through hole part using the resist 209 as the mask. At this time, isotropic etching is applied for etching of the wiring material 208, and by holding properly the margin of the resist 209 between the through hole opening part, the shape buried the opening part with the wiring material 210 can be formed, and the surface can be flattened.
AbstractList PURPOSE:To connect between a lower layer wiring and an upper layer wiring with a wiring material buried in a through hole, to enhance yield of a wiring system, and moreover to hold the upper part of the through hole flat by a method wherein the PR process is supplemented by one process per one wiring layer. CONSTITUTION:After a lower layer wiring 201 is formed on a semiconductor substrate 205, an interlayer insulating film 202 is adhered, the interlayer insulating film is etched using a resist 207 as the mask to open a through hole 206. At this time, the wiring material 208 of nearly the same thickness with the film 202 is adhered, and a resist 209 is formed only on the through hole. Then the wiring material 208 is removed leaving the through hole part using the resist 209 as the mask. At this time, isotropic etching is applied for etching of the wiring material 208, and by holding properly the margin of the resist 209 between the through hole opening part, the shape buried the opening part with the wiring material 210 can be formed, and the surface can be flattened.
Author MIZUSHIMA KAZUYUKI
Author_xml – fullname: MIZUSHIMA KAZUYUKI
BookMark eNrjYmDJy89L5WRQ9nX0C3VzdA4JDXJV8HdTCHb19XT293MJdQ7xD1JwcQ3zdHblYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgHBphaGFibmJkaOxsSoAQBOxyTt
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID JPS58184742A
GroupedDBID EVB
ID FETCH-epo_espacenet_JPS58184742A3
IEDL.DBID EVB
IngestDate Fri Jul 19 11:52:10 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_JPS58184742A3
Notes Application Number: JP19820067781
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19831028&DB=EPODOC&CC=JP&NR=S58184742A
ParticipantIDs epo_espacenet_JPS58184742A
PublicationCentury 1900
PublicationDate 19831028
PublicationDateYYYYMMDD 1983-10-28
PublicationDate_xml – month: 10
  year: 1983
  text: 19831028
  day: 28
PublicationDecade 1980
PublicationYear 1983
RelatedCompanies NIPPON DENKI KK
RelatedCompanies_xml – name: NIPPON DENKI KK
Score 2.3631933
Snippet PURPOSE:To connect between a lower layer wiring and an upper layer wiring with a wiring material buried in a through hole, to enhance yield of a wiring system,...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title MANUFACTURE OF SEMICONDUCTOR DEVICE
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19831028&DB=EPODOC&locale=&CC=JP&NR=S58184742A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5qFfWmVan1QUTJLdi8m0OQdJNQA3nQJqW3ku5mQQ-12Ih_39nYWi96W3Zhdnfgm9mZnQfAg84ptTWmKrzPKsWoOEKKilqEDuOWblWoA4VrIE6sUWFEM3PWgtdtLkxTJ_SzKY6IiKKI97qR16udE8tvYivXj4sXnHp7CnPXl9l3upjomqUNZH_oBlnqp0QmxI0yORm7ExM1k4F2oLcH-_iMtgUagulQZKWsfquU8AQOMqS2rE-hVS07cES2ndc6cBhvPrxxuMHe-gzuYy8pQo-IOAUpDaWJ4GCa-AXJ07HkB9NnEpzDXRjkZKTgbvOfq82jbHcw_QLaaPJXXZBUW2V9x-YO5ZbBSlbaon25blFHLReaSS-h9zed3n-LV3As2CSkrza4hnb9_lHdoFqtF7cNP74AbY54qg
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT8JAEJ4gGvGmqEF81Wh6a6QPWnpoTNm2AaSPQEu4NWW3TfSARGr8-85WEC962-wms7uTfDM7s_MAeFALSg2FyVLRYbmk5QVCivJahCYrdFXPUQdy14Af6INEG8278xq8bnNhqjqhn1VxREQURbyXlbxe7ZxYThVbuX5cvODU25MXW47IvtPFeNcspSc6fcuNQickIiHWKBKDiTXtombS0A6092Afn9gGR4M76_OslNVvleIdw0GE1JblCdTyZRMaZNt5rQmH_ubDG4cb7K1P4d63g8SzCY9TEEJPmHIOhoGTkDicCI47GxL3DO48NyYDCXdLf66WjqLdwdRzqKPJn7dAkA2ZdUyjMGmhayxjmcHbl6s6NeVsoXTpBbT_ptP-b_EWGoPYH6fjYfB8CUecZVwSK70rqJfvH_k1qthycVPx5gtAPnud
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=MANUFACTURE+OF+SEMICONDUCTOR+DEVICE&rft.inventor=MIZUSHIMA+KAZUYUKI&rft.date=1983-10-28&rft.externalDBID=A&rft.externalDocID=JPS58184742A