MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE:To provide a low resistance part or a high resistance part to the titled device, by providing an energy beam reflecting mask on a poly Si pattern, irradiating the beam, and activating ion implanted impurities. CONSTITUTION:An FET is formed by a conventional method. By a high resistance poly...

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Bibliographic Details
Main Authors NAKASE MAKOTO, YANASE TOSHINOBU
Format Patent
LanguageEnglish
Published 04.08.1983
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Summary:PURPOSE:To provide a low resistance part or a high resistance part to the titled device, by providing an energy beam reflecting mask on a poly Si pattern, irradiating the beam, and activating ion implanted impurities. CONSTITUTION:An FET is formed by a conventional method. By a high resistance poly Si layer 12, a poly Si gate 61 and a poly Si wiring 62 on a field oxide film 3 are connected. Then, an Al mask 21 is provided, P ions are implanted in the layer 12, the entire surface is irradiated by a laser beam, and the P ions are activated. The laser beam is reflected by the Al, and the implanted part of P is selectively heated. The gate electrode 61 and a high resistance layer 221 are not heated at all. Therefore, the low resistance part is not formed by the infiltration of P into the electrode 61 and the layer 221, and a wiring 22 having load resistance 221 as designed and a low resistance part 222 for a VDD wire is obtained. It is effective when P, As, and B are used for obtaining the low resistance and N, O, and Ar are used for obtaining the high resistance.
Bibliography:Application Number: JP19820012310