DMA DATA TRANSFER SYSTEM

PURPOSE:To reduce a load on a CPU by decreasing the frequency of interruption to the CPU due to DMA transfer with regard to an input and output equipment whose amount of data transferred once is small and where data are generated at random. CONSTITUTION:The main memory 3 of a CPU1 is enabled to be r...

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Bibliographic Details
Main Authors YASUMOTO SEIICHI, SATOU HIDEYA
Format Patent
LanguageEnglish
Published 09.04.1982
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To reduce a load on a CPU by decreasing the frequency of interruption to the CPU due to DMA transfer with regard to an input and output equipment whose amount of data transferred once is small and where data are generated at random. CONSTITUTION:The main memory 3 of a CPU1 is enabled to be referred to freely and directly from an input-output controller IOC2. In an optional address of the main memory 3, a control information storage area 4 for DMA data transfer is provided and a DMA data transfer permission flag is set there; and the permission flag for control information is read at a constant period, and according to the condition establishment of the DMA data transfer permission flag, asynchronous data transfer from the IOC2 to the main memory 3 of the CPU1 is achieved without any start command from the CPU1. Therefore, the frequency of interruption to the CPU1 due to the DMA transfer is decreased to reduce a load on the CPU1.
Bibliography:Application Number: JP19800134357