AUTOMATIC LAYOUT WIRING DEVICE, METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND STORAGE MEDIUM LOADED THEREWITH

• Main Author: OKADA NOBUYA
• Format: Patent
• Language: English
• Published: 29.10.1999
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To enable a semiconductor integrated circuit to be lessened in dead space and improved in degree of integration, to reduce a manual operation carried out by an operator's hands so as to finish a design in a shorter time for a semiconductor integrated circuit, and to reduce operation failures. SOLUTION: An automatic layout wiring method of a semiconductor integrated circuit comprises a first step A1 where each of grouped wiring regions is indicated, a second step A2 where a second circuit which is designated and grouped in the first step A1 is automatically disposed in a prescribed arrangement region, a third step A3 where a power supply wiring is provided to the second circuit disposed in the second step A2, a fourth step A4 where a prescribed range which includes the above arrangement region is designated as an arrangement forbidden region where a following circuit is forbidden to be arranged, a fifth step A5 where a power supply wiring is provided to the first circuit driven by a primary power supply system, a sixth step A6 where the first circuit is automatically arranged, and a seventh step A7 where all wirings except the power supply wirings are automatically installed.