NONVOLATILE SEMICONDUCTOR STORAGE AND ITS TEST METHOD

• Main Authors: NODA TOSHIFUMI, HONDA HIDENORI
• Format: Patent
• Language: English
• Published: 15.10.1999
• Edition: 6
• Subjects: INFORMATION STORAGE; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; STATIC STORES; TESTING

PROBLEM TO BE SOLVED: To perform correct decision and to shorten a test time by holding the data '1' in a sense latch circuit that the data '1' are read out temporarily with selection of a defect storage element all the time thereafter and outputting the hold data of the sense latch circuit to the outside after plural word lines are selected. SOLUTION: When even only one memory cell of the state that a threshold value isn't lowered to 2V or below is read out while prescribed steps are repeated related to all sectors, since a voltage of a main bit line DL is in a pre-charge level as it is, the data latched by the sense latch circuit SLT become the '1'. A bit line is charged by these data at the next-out time, and since the hold data of the sense latch circuit, that is, the former read-out data are OR operated with the next read-out data on the bit line, the data '1' are held in the sense latch circuit that the data '1' are read out temporarily by the selection of the defect memory cell all the time thereafter.