SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To eliminate erroneous recognition due to the inconveniences of a test circuit by judging whether the test circuit for executing a test mode is normally operating or not. SOLUTION: An entry signal for indicating a registered test mode is outputted from a test entry circuit 2, a...

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Bibliographic Details
Main Author KOZUKA EIJI
Format Patent
LanguageEnglish
Published 31.08.1999
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
STATIC STORES
TESTING
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Summary:PROBLEM TO BE SOLVED: To eliminate erroneous recognition due to the inconveniences of a test circuit by judging whether the test circuit for executing a test mode is normally operating or not. SOLUTION: An entry signal for indicating a registered test mode is outputted from a test entry circuit 2, and a test signal for executing the above test mode is generated by a test signal generation circuit. Then, an evaluation circuit 10 evaluates whether the above entry signal being outputted from the test entry circuit 2 is a signal for indicating the above test mode or not and whether the above test signal being generated from the test signal generation circuit is a signal for executing the above test mode or not.
Bibliography:Application Number: JP19980038772