SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

PROBLEM TO BE SOLVED: To reduce a local surface step which is required or forming a contact between wiring layers and is generated by an offset insulating layer in a semiconductor device having multilayer wiring. SOLUTION: A polycide wiring layer constituted of an amorphous silicon layer 13 and a tu...

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Bibliographic Details
Main Author UEJIMA MASAHIRO
Format Patent
LanguageEnglish
Published 18.06.1999
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To reduce a local surface step which is required or forming a contact between wiring layers and is generated by an offset insulating layer in a semiconductor device having multilayer wiring. SOLUTION: A polycide wiring layer constituted of an amorphous silicon layer 13 and a tungsten silicide layer 14, and the offset insulating layer 15 are formed on a substrate 11. The offset insulating layer 15 of a peripheral circuit part (b) where an interval between gate electrodes is wide is selectively removed. An oxide layer film (BPSG(borrow phosphor silicate glass) layer 18) of reflow ability is formed on an upper layer and the surface of the BPSG layer 18 is flattened by high temperature treatment.
Bibliography:Application Number: JP19970328835