INFORMATION PROCESSOR

PROBLEM TO BE SOLVED: To provide an information processor for guaranteeing correct execution of an instruction, especially at the time of logical disconnection between a host device and a slave device for in the information processor for receiving the instruction from the host device, storing it in...

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Bibliographic Details
Main Author HIROSE KIYOSHI
Format Patent
LanguageEnglish
Published 30.04.1999
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To provide an information processor for guaranteeing correct execution of an instruction, especially at the time of logical disconnection between a host device and a slave device for in the information processor for receiving the instruction from the host device, storing it in a buffer memory and executing plural instructions in parallel at the same time. SOLUTION: A detection part 12 detects whether or not a 1st host device 2 or 2nd host device 3 and a logical connection part 11 inside an information processor 1 are connected logically normally. When the detection part 12 detects any abnormality, an instruction invalidating part 13 outputs an invalidating instruction for invalidating the instruction in an instruction buffer 14 to the instruction buffer 14, and the return from an instruction executed result returning part 16 to the 1st host device 2 or 2nd host device 3 is inhibited.
Bibliography:Application Number: JP19970282181