MICROPROCESSOR REQUEST PIPELINE

PROBLEM TO BE SOLVED: To enable efficient processing while relaxing traffic on a processor bus by intelligently limiting the flow of interruption information through the bus between a microprocessor and a processor interface chip(PIC). SOLUTION: On a PIC 16, a write request is inputted to a register...

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Bibliographic Details
Main Authors RECTOR RUSSELL M, SABERNICK FRED C, RAHMAN MIZANUR M, GROSZ MARTIN J, FU PETER, SPROUSE JEFF A
Format Patent
LanguageEnglish
Published 04.12.1998
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To enable efficient processing while relaxing traffic on a processor bus by intelligently limiting the flow of interruption information through the bus between a microprocessor and a processor interface chip(PIC). SOLUTION: On a PIC 16, a write request is inputted to a register PTAIL 204(1) and write data are collected from a Dbus to a write buffer 208. When the buffer 208 is full, a full/empty flag 209 is set to 'full'. When the prescribed amount of data are loaded to the buffer 208, a controller 206 moves the write request from the PTAIL 204(1) to a register PHEAD 204(2). When an Ibus 26 can be used, the write request is moved there and the full/empty flag 209 is set to 'empty'. Therefore, since the write request or the like is asserted on the PIC 16 only at complete time, the Ibus 26 is efficiently used.
Bibliography:Application Number: JP19980147066