EVEN-NUMBERED AND ODD-NUMBERED FREQUENCY DIVISION CIRCUIT

• Main Author: IWASAKI MITSUHARU
• Format: Patent
• Language: English
• Published: 13.10.1998
• Edition: 6
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

PROBLEM TO BE SOLVED: To selectively generate the even-numbered frequency division clocks and odd-numbered frequency division clocks of a duty factor 50% practically in a simple circuit suitable for being made into an IC by validating a first logic circuit corresponding to control signals, obtaining pulses for which input clocks are frequency divided into even numbers from rear stage output, validating a second logic circuit corresponding to the control signals and obtaining the pulses for which the input clocks are frequency divided into odd numbers from a third logic circuit. SOLUTION: The pulses to be delayed for the half cycle of the input clocks are generated by latching the output signals of a Johnson counter 1 in the signals of the center position of one cycle of the input clocks CLK by a flip-flop 2. Then, in the case that the output signals of the Johnson counter 1 are lost, output for extending the output for the half cycle is obtained from the flip-flop 2. As a result, the even-numbered and odd-numbered clocks of the duty factor 50% are obtained in the simple circuit, the need of an exterior capacitor or the like is eliminated and an even-numbered and odd-numbered frequency division clock generation circuit suitable for being made into the IC is realized.