INFORMATION PROCESSOR

PROBLEM TO BE SOLVED: To provide information on the occurrence frequency of parity errors while the deterioration of the system performance is suppressed. SOLUTION: Data which are read from an instruction cache 3 or a data cache 4 by an instruction execution part 2 are parity-checked in a parity err...

Full description

Saved in:
Bibliographic Details
Main Authors IMON TOKUYASU, KAMATA EIKI, YAMAGATA MAKOTO
Format Patent
LanguageEnglish
Published 25.09.1998
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:PROBLEM TO BE SOLVED: To provide information on the occurrence frequency of parity errors while the deterioration of the system performance is suppressed. SOLUTION: Data which are read from an instruction cache 3 or a data cache 4 by an instruction execution part 2 are parity-checked in a parity error circuit 5 and the occurrence of the parity error is informed to the instruction execution part 2 and a frequency measuring circuit 7. The frequency measuring circuit 7 counts the number of occurrence times of the parity errors and resets a count value whenever an interval designated by the instruction execution part 2 elapses. A comparison circuit 8 compares a threshold which is set in a report threshold holding circuit 6 from the instruction execution part 2 with the count value of the frequency measuring circuit 7. When the count value exceeds the threshold, it is informed to the instruction execution part 2.
Bibliography:Application Number: JP19970078870