MANUFACTURE SEMICONDUCTOR DEVICE

• Main Author: UMEBAYASHI HIROSHI
• Format: Patent
• Language: English
• Published: 21.07.1998
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To reduce a chip area by a method, wherein a first contact hole is formed and embedded with an interlayer insulating film, a capacitor is formed, the interlayer insulating film is removed, then a conductive material is embedded and the interlayer insulating film, a second contact hole, etc., are formed. SOLUTION: First layer wirings 31, an interlayer insulating film 22 and second layer wirings 32 are formed to a substrate 10, and covered with an interlayer insulating film 23. Next, first contact holes CT1 are formed, an interlayer insulating film 24, etc., are deposited to bury the first contact holes CT1, and an interlayer film 25 is further deposited. A storage node contact is formed, and first layer conductive layers 31 and insulating films 26 for a capacitor are formed. A fourth layer conductive layer 34 and an interlayer insulating film 27 are shaped, the interlayer film 25 is removed, and the interlayer insulating film 24 is further taken off. The first contact holes CT1 are opened again, and blanket tungsten 35 is formed. An interlayer insulating film 29 is formed, a second contact hole CT2 is opened, ad a metallic wiring 36 is formed.