IMPROVED WIRING STRUCTURE FOR HIGHLY EFFICIENT CHIP

• Main Authors: FOLBERTH HARALD, KORTE BERNHARD PROF DR, KOEHL JUERGEN DR, KLINK ERICH
• Format: Patent
• Language: English
• Published: 30.06.1998
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To attenuate the inductive coupling and capacitive coupling between the conductors in each wiring layer by a method wherein each wiring direction of a plurality of wiring layers, which are stacked in multilayer, is rotated at the prescribed angle against the wiring direction of the wiring layer to be arranged in an induction and capacitive coupling region. SOLUTION: The wiring structures IIa and IIb, having seven superposed metal layers M0 to M6, which are superposed in multilayer, are formed by rotating at 45 deg. to 90 deg. with each other against the wiring direction of the wiring layer arranged in the relating inductive coupling region and a capacitive coupling region. Also, a wiring structure IIc, which is exceptional to the above- mentioned wiring structures IIa and IIb, is not interferentially coupled between the wiring structures of the metal layers M1 and M2 on the metal layers M3, M4, M5 and M6, and low interferential voltage, which can be neglected, is grown. As a result, the inductive coupling and the capacitive coupling between the conductors in each wiring layer can be lessened, and a highly efficient chip can be obtained.