PAT PAIR BIT CORRESPONDING INFORMATION CARD

PROBLEM TO BE SOLVED: To essentially prevent falsification forgery and illegal use with low costs by forming a pat pair about which an upper pat is molded on the opposite position to an under pat in the same method. SOLUTION: A metallic electrode layer of an under pat pattern electrode 2 is formed b...

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Bibliographic Details
Main Author UEDA SUKENORI
Format Patent
LanguageEnglish
Published 29.05.1998
Edition6
Subjects
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Summary:PROBLEM TO BE SOLVED: To essentially prevent falsification forgery and illegal use with low costs by forming a pat pair about which an upper pat is molded on the opposite position to an under pat in the same method. SOLUTION: A metallic electrode layer of an under pat pattern electrode 2 is formed by means of vapor deposition, sputter, printing, etc., on a card base material 1, and also, an insulating layer (or a resistance layer) 4 is applied in the form of leaving a detection electrode. Furthermore, a facing upper pat pattern electrode 3 is formed at the opposite position to the electrode 2 in the same means and has a structure that holds information of pat pair bit correspondence. Data is recorded by the pair of the pats, data that becomes unnecessary to read data is destroyed by heating, electric or mechanical means and a bit state can be fixed. Because the information fixed state is carried out inside the pat pair, it is impossible to externally return it to an insulating state again and then, it is impossible to perform falsification, forgery, etc., of a used card.
Bibliography:Application Number: JP19960314148