PSEUDO-CACHE DRAM CONTROLLER HAVING PACKET COMMAND PROTOCOL

PROBLEM TO BE SOLVED: To provide a DRAM controller for utilizing the performance of pseudo- cache DRAM to the maximum by reducing overhead thereby enhancing the processing rate. SOLUTION: A DRAM controller 10 issues an immediately preceding memory access request and a current memory access request t...

Full description

Saved in:
Bibliographic Details
Main Author SHU YUNG LEE
Format Patent
LanguageEnglish
Published 15.05.1998
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:PROBLEM TO BE SOLVED: To provide a DRAM controller for utilizing the performance of pseudo- cache DRAM to the maximum by reducing overhead thereby enhancing the processing rate. SOLUTION: A DRAM controller 10 issues an immediately preceding memory access request and a current memory access request to a DRAM 14 having a memory array and an output buffer. The controller 10 has a communication protocol between the controller 10 and the DRAM 14. The protocol includes a signal indicative of the state of memory array corresponding to the immediately preceding memory access request formed by the DRAM 14.
Bibliography:Application Number: JP19970041887