COMPARE-AND-SWAP CONTROL SYSTEM

PROBLEM TO BE SOLVED: To prevent an intermittent fault of the interface set between a shared memory device and a CPU from affecting the exclusive control of the shared memory that is performed by the C.S.(compare-and-swap). SOLUTION: The error caused on the interface of a replay given from a shared...

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Bibliographic Details
Main Authors YANAGISAWA YASUSHI, KANAMARU TOMOYUKI, HIROSE KIYOSHI
Format Patent
LanguageEnglish
Published 15.05.1998
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To prevent an intermittent fault of the interface set between a shared memory device and a CPU from affecting the exclusive control of the shared memory that is performed by the C.S.(compare-and-swap). SOLUTION: The error caused on the interface of a replay given from a shared memory device 2 is detected by a C.S. instruction reply error detection means 5 in a C.S. instruction mode, and the C.S. instruction is retried by a C.S. instruction retry means 3. This retry of the C.S. instruction is notified by a C.S. instruction retry notification means 4. Then, a C.S. instruction reply stack means 9 of the device 2 stacks the replay in a C.S. instruction execution mode. When a C.S. instruction retry decision means 7 decides a C.S. instruction of retry, a C.S. operation suppression means 8 suppresses the C.S. operation. Then, 'reply of C.S. instruction execution mode' that is stacked by the means 9 is returned to a CPU 1 by a stack replay sending means 10.
Bibliography:Application Number: JP19960282125