SEMICONDUCTOR MEMORY DEVICE WITH VARIABLE PLATE VOLTAGE GENERATION CIRCUIT

PROBLEM TO BE SOLVED: To enhance the sensing rate at low voltage by boosting the voltage level at the storage node of a designated memory cell forcibly through a plate voltage generation circuit. SOLUTION: A plate voltage of VCC level is fed to the plate node of a memory cell through the channel of...

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Bibliographic Details
Main Authors JO TOICHI, RI SOUFU
Format Patent
LanguageEnglish
Published 07.02.1997
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To enhance the sensing rate at low voltage by boosting the voltage level at the storage node of a designated memory cell forcibly through a plate voltage generation circuit. SOLUTION: A plate voltage of VCC level is fed to the plate node of a memory cell through the channel of a PMOS transistor 48 prior to charge sharing between the memory cell and a bit line. The voltage level at a storage node from 0V to 1/2VC and from VCC to 3/2VCC, respectively, when the state of a data stored in the memory cell is low and high. Consequently, the sensing operation is carried out at high rate in a semiconductor memory device with a variable plate voltage generation circuit without requiring any increase of element due to the overvoltage at the time of access operation when the voltage level at storage node is boosted through the variable plate voltage generation circuit.
Bibliography:Application Number: JP19960174003