SYSTEM CLOCK RECOVERY CIRCUIT FOR DIGITAL BROADCAST RECEIVER

PROBLEM TO BE SOLVED: To obtain a system clock recovery device with an inexpensive configuration by which an incorrect system clock recovery is prevented caused on the occurrence of a fault of program clock reference(PCR) reception. SOLUTION: A converged value of a control voltage of a voltage contr...

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Bibliographic Details
Main Author KAWABATA YOHEI
Format Patent
LanguageEnglish
Published 02.12.1997
Edition6
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:PROBLEM TO BE SOLVED: To obtain a system clock recovery device with an inexpensive configuration by which an incorrect system clock recovery is prevented caused on the occurrence of a fault of program clock reference(PCR) reception. SOLUTION: A converged value of a control voltage of a voltage controlled crystal oscillator(VCXO) 1140 when a PCR reception is normal is calculated and stored by a fixed value generator 2140 and in the event of detecting a fault of PCR reception by a PCR error detector 2100, the control voltage of the VCXO 1140 is immediately replaced with the output of the fixed value generator 2140 to continue regular system clock recovery.
Bibliography:Application Number: JP19960126754