MEMORY MODULE

PROBLEM TO BE SOLVED: To provide a memory module which can reduce manufacturing costs. SOLUTION: If each bit to terminals DQ0'-DQ2' of each of memory elements 1-3 is not defective, selected pads 5a-5c and selection pads 5d-5f of each jumper chip loaded pad 5 are connected together by each...

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Bibliographic Details
Main Author USHIDA YOICHI
Format Patent
LanguageEnglish
Published 31.10.1997
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To provide a memory module which can reduce manufacturing costs. SOLUTION: If each bit to terminals DQ0'-DQ2' of each of memory elements 1-3 is not defective, selected pads 5a-5c and selection pads 5d-5f of each jumper chip loaded pad 5 are connected together by each of jumper chips 6, and the terminals DQ0'-DQ2' of each of the memory elements 1-3 are connected to an external substrate terminal 4. If any of the bits are defective, corresponding pads 5g-5i are connected to the selected pads 5a-5c instead of the selection pads 5d-5f, to which the terminals DQ0'-DQ2' corresponding to defective bits are connected. And terminals DQ3' of corresponding memory elements 1-3 are connected to the external substrate terminal.
Bibliography:Application Number: JP19960089137