ACS ARITHMETIC UNIT

PROBLEM TO BE SOLVED: To reduce a circuit scale by providing a decode circuit decoding the comparison result and an overflow detection signal and a selection circuit with clip processing conducting altogether the selection of sum results and clip processing based on a control signal outputted from t...

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Bibliographic Details
Main Author NAKAI YUJI
Format Patent
LanguageEnglish
Published 19.09.1997
Edition6
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To reduce a circuit scale by providing a decode circuit decoding the comparison result and an overflow detection signal and a selection circuit with clip processing conducting altogether the selection of sum results and clip processing based on a control signal outputted from the decode circuit. SOLUTION: An adder 101 executes the calculation of PMA[4:0]+BMA[4:0] and an adder 102 executes the calculation of PMB[4:0]+BMB[4:0]. Then an overflow detection circuit 104 detects an overflow at the addition and a comparator 103 compares the quantity of the addition results. Succeedingly a decoder circuit 105 decodes overflow detection signals OA, OB and a comparison result CP and a clip processing including selection circuit 106 selects the result of sum which is smaller in the results. In the case that the selected sum result is overflow data, clip processing is applied to the data. Then the clip processing including selection circuit 106 is controlled by the decoder circuit 105 to conduct selection of the sum result and the clip processing altogether.
Bibliography:Application Number: JP19960051253