SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To make it possible to make low a lead inductance in a semiconductor device and to obtain a large capacitance by a method wherein the first terminal of a second planar conductor and a ground terminal are connected with each other. SOLUTION: A first terminal 31-1 of a second pla...

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Bibliographic Details
Main Authors MATSUNAGA HAYASHI, IWATA MASAO
Format Patent
LanguageEnglish
Published 19.08.1997
Edition6
Subjects
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Summary:PROBLEM TO BE SOLVED: To make it possible to make low a lead inductance in a semiconductor device and to obtain a large capacitance by a method wherein the first terminal of a second planar conductor and a ground terminal are connected with each other. SOLUTION: A first terminal 31-1 of a second planar conductor 31 and a ground terminal 29 are connected with each other via a wiring pattern 35 and bonding pads 26-1 for signal input/output use on an IC die 26 are connected with signal input/output terminals 27 through a wiring pattern 35 which is provided on a substrate 25. A dielectric material 32 is held between planar conductors 30 and 31, is superposed on the conductor 31 to constitute a capacitor and at the same time, a power current is made to flow through the conductor 30 going through a first terminal 30-1 of a first planar conductor from a power terminal 28. A return current is made to flow through the conductor 31 going through a second terminal 31-2 of the conductor 31 from a bonding pad 26-3 for grounding use of the die 26. Moreover, as the return current is made to flow to the terminal 29 via the terminal 31-1 of the conductor 31, the capacitor provides a distributed capacitance to a current path and noise can be passed in a wide band.
Bibliography:Application Number: JP19960026387