PARALLEL/SERIAL CONVERSION CIRCUIT
PROBLEM TO BE SOLVED: To provide the parallel/serial conversion circuit from which data of a stable serial signal are outputted. SOLUTION: When parallel signal data are received by a data input terminal DATA, the data are latched and inverted by a leading of a latch clock signal received by a latch...
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Main Author | |
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Format | Patent |
Language | English |
Published |
11.07.1997
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To provide the parallel/serial conversion circuit from which data of a stable serial signal are outputted. SOLUTION: When parallel signal data are received by a data input terminal DATA, the data are latched and inverted by a leading of a latch clock signal received by a latch clock signal input terminal RCK. Then the data are counted based on a clock signal received by the clock input terminal CLK1 and when the count reaches a prescribed value, a ripple carry signal is outputted from a ripple carry signal output terminal RCY. A D flip-flop circuit 2 keeps an output of a serial signal received at a data input terminal D from a data output terminal OUT till the ripple carry signal is received by a reset terminal R. |
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Bibliography: | Application Number: JP19950340656 |