HIGH SPEED DATA TAKE-IN DEVICE AND IC TEST DEVICE

PROBLEM TO BE SOLVED: To enable writing data in a shorter access time than a memory with a long access time by using the memory and speedily writing the same data simultaneously in each fail memory without performing an interleave correction operation. SOLUTION: This device is provided with a data h...

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Bibliographic Details
Main Author FUKUZAKI TADASHI
Format Patent
LanguageEnglish
Published 10.06.1997
Edition6
Subjects
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Summary:PROBLEM TO BE SOLVED: To enable writing data in a shorter access time than a memory with a long access time by using the memory and speedily writing the same data simultaneously in each fail memory without performing an interleave correction operation. SOLUTION: This device is provided with a data holding means at each data input terminal of memories 57a to 57d. Each data holding means holds data supplied in turn from a data supply means synchronizing with a high speed clock for one cycle time of a low speed clock at a timing synchronizing with the low speed clock with a different timing. A timing generation means 53 outputs in turn the low speed clock obtained by dividing the frequency of the high speed clock into M, with a delay of one cycle time, to the data holding means. Therefore, data is held in each data holding means with different timing in turn. The timing generation means 53 outputs the right enable signals to the memories 57a to 57d after all the data holding means hold the data.
Bibliography:Application Number: JP19950335801