CMOS DIFFERENTIAL AMPLIFIER CIRCUIT

• Main Authors: SUGANUMA MASANORI, NACHI SHIKIKO, YAMAMOTO MOROHISA, NAKAUCHI ATSUHIKO
• Format: Patent
• Language: English
• Published: 16.05.1997
• Edition: 6
• Subjects: AMPLIFIERS; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

PROBLEM TO BE SOLVED: To reduce the changes of both gain and phase frequency characteristics and to secure the satisfactory DG(differential gain) and DP(differential phase) characteristics by regulating the larger one of both currents amplified by a 1st or 3rd current mirror circuit by the other smaller current. SOLUTION: When a pair of input signals V (+) and V (-) are set at the same level, the voltage of the same level as these input signals is outputted to an output terminal OUT. If the potential of the signal V (+) rises under such conditions, the current I1 flowing to a MOS transistor TR MN9 increases and the current I2 flowing to a TR MN10 reduces. Therefore, the gate voltage of a MOS TR MP7 placed at the output side of a 1st current mirror circuit 23 rises to try to increase the drain current of the TR MP7. Thus the on- resistance of the TR MP7 reduces. Then the gate voltage of a MOS TR MN13 of a 3rd current mirror circuit 24 drops to try to reduce the drain current of the TR MN13. Thus the on-resistance of the TR MN13 increases. As a result, the output voltage rises.